多芯片小数分频锁相环输出信号相位同步设计
Design of multi chip fractional frequency phase locked loop output signal phase synchronization
多芯片小数分频锁相环输出信号相位同步设计 |
| 徐砚天,黄晓敏,李浩明,王志宇,郁发新 |
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Design of multi chip fractional frequency phase locked loop output signal phase synchronization |
| Yan-tian XU,Xiao-min HUANG,Hao-ming LI,Zhi-yu WANG,Fa-xin YU |
| 图 5 相位同步前2个PLL输出信号 |
| Fig.5 Two PLL output signal before phase synchronization |
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