多芯片小数分频锁相环输出信号相位同步设计 |
徐砚天,黄晓敏,李浩明,王志宇,郁发新 |
Design of multi chip fractional frequency phase locked loop output signal phase synchronization |
Yan-tian XU,Xiao-min HUANG,Hao-ming LI,Zhi-yu WANG,Fa-xin YU |
图 4 相位差计算结果的误差随累加采样点数变化曲线 |
Fig.4 Error curve of phase difference calculation results with accumulated sampling points |
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