采用0.18 μm CMOS工艺的高速模拟自适应判决反馈均衡器
High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology
采用0.18 μm CMOS工艺的高速模拟自适应判决反馈均衡器 |
| 展永政,胡庆生 |
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High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology |
| Yong-zheng ZHAN,Qing-sheng HU |
| 图 4 D 触发器 (DFF)原理图 |
| Fig.4 D flip-flop (DFF) schematic |
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