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浙江大学学报(工学版)
Journal of ZheJiang University (Engineering Science)  2021, Vol. 55 Issue (9): 1788-1794    DOI: 10.3785/j.issn.1008-973X.2021.09.021
    
Design of multi chip fractional frequency phase locked loop output signal phase synchronization
Yan-tian XU1(),Xiao-min HUANG2,Hao-ming LI2,Zhi-yu WANG1,*(),Fa-xin YU1
1. College of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China
2. Hangzhou Chengxin Technology Limited company, Hangzhou 310030, China
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Abstract  

An algorithm of fractional frequency phase locked loop (PLL) output signal phase synchronization was proposed, in order to realize the phase synchronization of PLL on multiple transceiver chips or a single transceiver chip in a multi-channel radio frequency (RF) communication system. A selection algorithm of sampling points for phase accumulation was designed. The sampling points selected by the algorithm were used to accumulate the triangulation results of PLL’s output signal under sampled by reference clock and reference signal generated by NC oscillator (NCO), so as to eliminate the high-order harmonic component and reduce the error of the phase difference calculation result effectively. According to the size of the phase difference, the fractional frequency ratio of the input of delta-sigma modulator (DSM) in PLL was adjusted by feedback, so that the phase of PLL output signal was adjusted linearly, and the phase synchronization of multiple PLL output signals with reference signal was realized. The correctness of the algorithm is verified by simulation, and the phase error is 0.35 ° after the final phase synchronization, and the time required to complete the synchronization is 210 ms.

Key words： fractional frequency phase locked loop      phase synchronization      multi-chip synchronization      multi-channel radio frequency communication      phase difference calculation     
Received: 09 September 2020      Published: 20 October 2021
CLC:  TN402  
Corresponding Authors: Zhi-yu WANG     E-mail: 21824063@zju.edu.cn;zywang@zju.edu.cn
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Yan-tian XU
Xiao-min HUANG
Hao-ming LI
Zhi-yu WANG
Fa-xin YU
Cite this article:

Yan-tian XU,Xiao-min HUANG,Hao-ming LI,Zhi-yu WANG,Fa-xin YU. Design of multi chip fractional frequency phase locked loop output signal phase synchronization. Journal of ZheJiang University (Engineering Science), 2021, 55(9): 1788-1794.

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https://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2021.09.021     OR     https://www.zjujournals.com/eng/Y2021/V55/I9/1788


多芯片小数分频锁相环输出信号相位同步设计

为了在多通道射频（RF）通信系统中，实现多个收发器芯片或单个收发器芯片上的锁相环（PLL）相位同步，提出小数分频PLL输出信号相位同步算法. 设计相位累加采样点数选取算法，算法选取的采样点数用于累加参考时钟欠采样的PLL输出信号与数控振荡器（NCO）产生的参考信号经三角运算的结果，以消除高次谐波分量，并有效降低相位差计算结果的误差. 根据相位差的计算结果反馈调节PLL内 delta-sigma 调制器(DSM)输入的小数分频比，线性调整PLL输出信号的相位，实现多个PLL输出信号相位与参考信号相位同步. 通过仿真验证算法的正确性，且最终相位同步后的相位误差为0.35°，完成同步所需的时间为210 ms.


关键词： 小数分频锁相环,  相位同步,  多芯片同步,  多通道射频通信,  相位差计算 
Fig.1 Basic structure of fractional frequency PLL and multi-chip PLL phase synchronization function diagram
Fig.2 Block diagram of fractional frequency PLL phase synchronization circuit
Fig.3 Variation curve of error sampling points with Ncal
Fig.4 Error curve of phase difference calculation results with accumulated sampling points
Fig.5 Two PLL output signal before phase synchronization
Fig.6 NCO output signal and its phase signal
Fig.7 Phase difference calculated by phase detector
Fig.8 Two PLL output signals after phase synchronization
Fig.9 Curve of phase difference with time between two PLL output signals
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