电子、通信与自动控制技术 |
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不同栅压下NMOS器件的静电防护性能 |
朱科翰,董树荣,韩雁,杜晓阳 |
(浙江大学 信电与电子工程学系,浙江 杭州 310027) |
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ESD protection of NMOS device at different gate bias |
ZHU Ke-han, DONG Shu-rong, HAN Yan, DU Xiao-yang |
(Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China) |
引用本文:
朱科翰, 董树荣, 韩雁, 等. 不同栅压下NMOS器件的静电防护性能[J]. J4, 2010, 44(1): 141-144.
SHU Ke-Han, DONG Shu-Rong, HAN Yan, et al. ESD protection of NMOS device at different gate bias. J4, 2010, 44(1): 141-144.
链接本文:
http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2010.01.025
或
http://www.zjujournals.com/eng/CN/Y2010/V44/I1/141
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[2] OH K H, DUVVURY C, BANERJEE K, et al. Gate bias induced heating effect and implications for the design of deep submicron ESD protection [C]∥ International Electron Devices Meeting. Washington: IEEE, 2001: 315-318.
[3] YANG C T, KER M D. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices [J]. IEEE Transactions on Device and Materials Reliability, 2001, 1(4): 190-203.
[4] LIOU J J, SALCEDO J A, LIU Z. Robust ESD protection solutions in CMOS/BiCMOS technologies [C]∥ Proceeding of 2007 International Workshop on Electron Devices and Semiconductor Technology. Beijing: IEEE, 2007: 41-45.
[5] ORTIZ-CONDE A, GARCIA-SANCHEZ F J, MUCI J, et al. A review of core compact models for undoped double-gate SOI MOSFETs [J]. IEEE Transactions on Electron Devices, 2007, 54(1): 131-140.
[6] WANG A Z H. On-chip ESD protection for integrated circuits: an IC design perspective [M]. New York: Kluwer Academic Publishers, 2002: 79-82.
[7] VOLDMAN S H. ESD: circuits and devices [M]. Vermont: John Wiley & Sons, 2006: 201-207. |
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