Electrical & Electronic Engineering |
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Low-complexity multiplexer-based normal basis multiplier over GF(2m) |
Jenn-Shyong HORNG, I-Chang JOU, Chiou-Yng LEE |
Institute of Engineering Science and Technology, National Kaohsiung First University of Science and Technology, Taiwan 811, Kaohsiung County; Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taiwan 333, Taoyuan County |
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Abstract We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular configurations and is well suited to VLSI implementations.
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Received: 26 May 2008
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