| Electrical & Electronic Engineering |
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| Test access to deeply embedded analog terminals within an A/MS SoC |
| NIARAKI Asli Rahebeh, MIRZAKUCHAKI Sattar, NAVABI Zainalabedin, RENOVELL Michel |
| College of Electrical and Computer Engineering, Iran University of Science and Technology, 16846-13114 Tehran, Iran; Electrical and Computer Engineering Department, University of Tehran, 14399 Tehran, Iran; Laboratoire d’informatique, Robotique et Microeiectronique de Montpelier (LIRMM), 161 Rue Ada, 34392 Montpellier Cedex 5, France |
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Abstract This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase accessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscillation-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscillation-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.
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Received: 05 June 2007
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