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Front. Inform. Technol. Electron. Eng.  2010, Vol. 11 Issue (8): 620-628    DOI: 10.1631/jzus.C0910500
    
A parallel and scalable digital architecture for training support vector machines
Kui-kang Cao1, Hai-bin Shen*,1, Hua-feng Chen2
1 Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China 2 Zhejiang University of Media and Communications, Hangzhou 310027, China
A parallel and scalable digital architecture for training support vector machines
Kui-kang Cao1, Hai-bin Shen*,1, Hua-feng Chen2
1 Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China 2 Zhejiang University of Media and Communications, Hangzhou 310027, China
 全文: PDF 
摘要： To facilitate the application of support vector machines (SVMs) in embedded systems, we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training SVMs. By taking advantage of the mature and popular SMO algorithm, the numerical instability issues that may exist in traditional numerical algorithms are avoided. The error cache updating task, which dominates the computation time of the algorithm, is mapped into multiple processing units working in parallel. Experiment results show that using the proposed architecture, SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be achieved. This architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications, and thus is more suitable for embedded use, where scalability is an important concern.
关键词： Support vector machine (SVM);  Sequential minimal optimization (SMO);  Field-programmable gate array (FPGA);  Scalable architecture       
Abstract: To facilitate the application of support vector machines (SVMs) in embedded systems, we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training SVMs. By taking advantage of the mature and popular SMO algorithm, the numerical instability issues that may exist in traditional numerical algorithms are avoided. The error cache updating task, which dominates the computation time of the algorithm, is mapped into multiple processing units working in parallel. Experiment results show that using the proposed architecture, SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be achieved. This architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications, and thus is more suitable for embedded use, where scalability is an important concern.
Key words: Support vector machine (SVM)    Sequential minimal optimization (SMO)    Field-programmable gate array (FPGA)    Scalable architecture
收稿日期: 2009-08-14 出版日期: 2010-08-02
CLC:  TN79  
基金资助: Project (No. 60720106003) supported by the National Natural Science Foundation of China 
通讯作者: Hai-bin SHEN     E-mail: shb@vlsi.zju.edu.cn
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Kui-kang Cao, Hai-bin Shen, Hua-feng Chen. A parallel and scalable digital architecture for training support vector machines. Front. Inform. Technol. Electron. Eng., 2010, 11(8): 620-628.

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http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C0910500    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2010/V11/I8/620

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