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Front. Inform. Technol. Electron. Eng.  2010, Vol. 11 Issue (6): 444-449    DOI: 10.1631/jzus.C0910381
    
Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
Di Li*,1, Yin-tang Yang1, Jiang-an Wang1,2, Bing Li1, Qiang Long1,2, Jary Wei2, Nai-di Wang2, Lei Wang2, Qian-kun Liu2, Da-long Zhang2
1 School of Microelectronics, Xidian University, Xi'an 710071, China 2 Huaxun Microelectronics Corporation, Xi'an 710075, China
Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer
Di Li*,1, Yin-tang Yang1, Jiang-an Wang1,2, Bing Li1, Qiang Long1,2, Jary Wei2, Nai-di Wang2, Lei Wang2, Qian-kun Liu2, Da-long Zhang2
1 School of Microelectronics, Xidian University, Xi'an 710071, China 2 Huaxun Microelectronics Corporation, Xi'an 710075, China
 全文: PDF(232 KB)  
摘要： A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and ?108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of ?130 dBm. The chip operates over a temperature range of [?40, 120] °C and ±5% tolerance over the CMOS technology process.
关键词： GPS receiver;  ΣΔ fractional-N synthesizer;  Image rejection;  Phase noise    
Abstract: A 19 mW highly integrated GPS receiver with a ΣΔ fractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure<2 dB, channel gain=108 dB (LNA1 included), image rejection>36 dB, and ?108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of ?130 dBm. The chip operates over a temperature range of [?40, 120] °C and ±5% tolerance over the CMOS technology process.
Key words: GPS receiver    ΣΔ fractional-N synthesizer    Image rejection    Phase noise
收稿日期: 2009-06-28 出版日期: 2010-06-02
CLC:  TN402  
基金资助: Project  supported  by  the  National  Natural  Science  Foundation  of China  (Nos.  60725415  and  60971066)  and  the  National  High-Tech
R & D Program (863) of China (Nos. 2009AA01Z258 and 2009AA 01Z260)
通讯作者: Di LI     E-mail: lidi2004@126.com
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Di Li
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Qiang Long
Jary Wei
Nai-di Wang
Lei Wang
Qian-kun Liu
Da-long Zhang

引用本文:

Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer. Front. Inform. Technol. Electron. Eng., 2010, 11(6): 444-449.

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http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C0910381    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2010/V11/I6/444

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