Abstract:In this paper, some theoretical analysis and an algorithm of automated synthesis of ternary T-gate combinational logic networks based on reduced disjoint sum-of-products forms of ternary logic functions are presented by using the fundamental operations and main properties of the ternary lattice algebra system with complement operation and ternary T-algebra system. An application example of the method is given. The ternary T-gate model and the ternary-gate combinational logic network in the application example are realized by using circuits of CMOS transistors. The correctness and the effectiveness of the logical function for the designed ternary T-gate combinational network is verified by the HSPICE simulation experiment. With this method, automated synthesis of ternary T-gate combinational logic networks can easily be accomplished on a computer.
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