Abstract：As the feature size of CMOS technology is scaled down, devices mismatch and process tolerance will lead to deviation in bandgap reference voltage, which significantly impacts manufacturing cost by decreasing yield. Based on the Pelgrom's mismatch model, this paper proposes a design methodology from three aspects: parameters, schematic and layout. Hspice simulation result shows that the output of the bandgap reference circuit is(1.232 54±0.005)V in CSMC 0.5 μm technology. Applying this design in 3 channels LED driver chips, the test results indicate that the yield reaches 96.8%, while the chips that meet the output current requirements of(18±0.5) mA account for above 99.6%.
俞淼, 罗小华, 卢宇峰, 李益航. 增强工艺偏差容忍度的带隙基准电压源设计[J]. 浙江大学学报（理学版）, 2016, 43(6): 689-695.
YU Miao, LUO Xiaohua, LU Yufeng, LI Yihang. Bandgap voltage reference design with enhanced tolerance of process variations. Journal of ZheJIang University(Science Edition), 2016, 43(6): 689-695.
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2016, Vol. 43 
