电子科学 |
|
|
|
|
多粒度通信优化的MPSoC调度映射策略 |
蔡田田1, 习伟1, 郭晓斌1, 姚浩1, 黄凯2 |
1. 南方电网科学研究院有限责任公司, 广东 广州 510080; 2. 浙江大学 信息与电子工程学院, 浙江 杭州 310027 |
|
MPSoC mapping and scheduling approach with multi-grained communication optimizations |
CAI Tiantian1, XI Wei1, GUO Xiaobin1, YAO Hao1, HUANG Kai2 |
1. Electric Power Research Institute, CSG, Guangzhou 510080, China; 2. College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China |
引用本文:
蔡田田, 习伟, 郭晓斌, 姚浩, 黄凯. 多粒度通信优化的MPSoC调度映射策略[J]. 浙江大学学报(理学版), 2017, 44(4): 429-436.
CAI Tiantian, XI Wei, GUO Xiaobin, YAO Hao, HUANG Kai. MPSoC mapping and scheduling approach with multi-grained communication optimizations. Journal of ZheJIang University(Science Edition), 2017, 44(4): 429-436.
链接本文:
https://www.zjujournals.com/sci/CN/10.3785/j.issn.1008-9497.2017.04.008
或
https://www.zjujournals.com/sci/CN/Y2017/V44/I4/429
|
[1] COTTON S, MALER O, LEGRIEL J, et al. Multi-criteria optimization for mapping programs to multi-processors[C]//IEEE International Symposium on Industrial&Embedded Systems.Vasteras:IEEE Computer Society, 2011:9-17. [2] FERRANDI F, LANZI P L, PILATO C, et al. Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems[J]. IEEE Trans Comput-Aided Des Integ Circuits & Syst,2010,29(6):911-924. [3] HUANG K, YU M, ZHANG X M, et al. ILP based multithreaded code generation for Simulink model[J]. IEICE Trans Inf & Syst,2014,97(12):3072-3082. [4] YAN R J, HUANG K, YU M, et al. Communication pipelining for code generation from Simulink models[C]//IEEE International Conference on Trust. Melbourne:IEEE Computer Society,2013,8(1):1893-1900. [5] BRISOLARA L, HAN S, GUERIN X L,et al. Reducing finegrain communication overhead in multithread code generation for heterogeneous MPSoC[C]//SCOPES'07. Nice:ACM,2007,11(1):81-89. [6] HAN S, CHAE S, BRISOLARA L, et al. Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC[J]. Des Autom Embed Syst,2007,11(4):249-283. [7] KAHN G, MACQUEEEN D. Coroutines and networks of parallel processors[C]//Proceedings of the IFIP Congress 77. Toronto:North-Holland Publishing Company,1977:993-998. [8] LEE E A, PARKS T M. Dataflow Process Networks[M]. Norwell:Kluwer Academic Publishers,2001,83(5):59-85. [9] MATHWORKS. Math works发布包含MATLAB和Simulink产品系列的Release2016b[ER/OL].http://www.mathworks.com/products/simulink.html. [10] HAN S I, CHAE S I, JERRAYA A A. Functional modeling techniques for efficient SW code generation of video codec applications[C]//ASP-DAC'06. Yokohama:ACM,2006,13(13):935-940. [11] HAN S I, CHAE S I, BRISOLARA L, et al. Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation[J].Integ VLSI J, 2009,42(2):227-245. [12] C-SKY, Inc. C-Sky IP authorization,2016[EB/OL] http://www.csky.com/solution/CPU-IP-shou-quan.htm. [13] HAN S I, BAGHDADI A, BONACIU M, et al. An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory[C]//DAC'04.SanDiego:IEEE,2004:250-255. |
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
|
Shared |
|
|
|
|
|
Discussed |
|
|
|
|