| Microelectronics |
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| Reliability assessment of networks-on-chip based on analytical models |
| Mojtaba VALINATAJ, Siamak MOHAMMADI, Saeed SAFARI |
| School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran 14395-515, Iran |
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Abstract As technology scales down, the reliability issues are becoming more crucial, especially for networks-on-chip (NoCs) that provide the communication requirements of multi-processor systems-on-chip. Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we accurately formulate the inherent reliability and vulnerability of some popular NoC architectures against permanent faults, also depending on the employed routing algorithm and traffic model. Based on this analysis, effects of failures in the links, switches and network interfaces on the packet delivery of NoCs are determined. Besides, some extensions to evaluate a fault-tolerant method and some routing algorithms are described. The analyses are validated through appropriate simulations. The results thus obtained are exactly the same as or very close to the analytical ones.
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Received: 09 December 2008
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