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浙江大学学报(工学版)  2017, Vol. 51 Issue (12): 2341-2347    DOI: 10.3785/j.issn.1008-973X.2017.12.005
计算机与通信技术     
基于FPGA的全数字时钟生成方法
徐盼盼, 张朝杰, 娄延年, 徐九凌
浙江大学 微小卫星研究中心, 浙江 杭州 310027
FPGA-based all-digital clock generation method
XU Pan-pan, ZHANG Chao-jie, LOU Yan-nian, XU Jiu-ling
Micro-satellite Research Center, Zhejiang University, Hangzhou 310027, China
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摘要:

由数控振荡器(NCO)生成的时钟存在严重的周期性边沿抖动,并且频域上存在较多的杂散信号.为此,在NCO的基础上引入抖动算法和锁相环技术,设计一种改进的全数字时钟生成方法.采用抖动算法产生随机数,并将随机数添加到NCO的数字相位输出端,使得时钟边沿随机提前,从而降低相位抖动的周期性,使杂散的功率均匀化分布到整个频域;利用锁相环技术滤除由于杂散的均匀化而增加的基底噪声.在Matlab中搭建仿真模型,生成几种不同频率的目标时钟,统计结果显示:采用该方法后时钟的相位抖动标准差显著降低.将本设计应用于Spartan-6 FPGA,实验结果表明:抖动算法可使杂散白化,锁相环技术可以降低基底噪声,滤除带外杂散.在与现有方法频率稳定度相近的情况下,所提方法输出的时钟信号频率精度大为提高,频率精度和稳定度分别达到7.5×10-9和2.5×10-9,并且所得到的时钟信号具有频率适应性.

Abstract:

The clock generated by numerically controlled oscillator (NCO) has severe periodic edge jitters, and there are many spurious signals in the frequency domain. Therefore, an improved all-digital clock generation method was designed, which combined dither algorithm and phase-locked loop technology with NCO. The dither algorithm was used to generate random numbers; the random numbers were added to the digital phase output of the NCO, so that the clock edge was randomly ahead of time. The periodicity of the phase jitters was reduced and the power of the spurious was uniformly distributed to the entire frequency domain. The phase-locked loop technology was used to filter out the increased base noise due to spurious homogenization. With the simulation model built in Matlab,several target clocks were generated with different frequencies. The statistical results show that the standard deviation of phase jitters is significantly reduced after using this method. The design was implemented on Spartan-6 FPGA, and the experimental results show that the spurious is whitened by dither algorithm and that the phase-locked loop technology can reduce the base noise and the filter out-of-band spurious. Compared with the existing methods under the similar frequency stability, the clock frequency accuracy is greatly improved by the proposed method. The frequency accuracy reaches 7.5 parts per billion and the frequency stability reaches 2.5 parts per billion; the clock signal generated by the proposed method has frequency adaptability.

收稿日期: 2017-03-22 出版日期: 2017-11-22
CLC:  TN96  
基金资助:

国家自然科学基金资助项目(61401389).

通讯作者: 张朝杰,男,副研究员.orcid.org/0000-0002-0905-3972.     E-mail: zhangcj@zju.edu.cn
作者简介: 徐盼盼(1993-),女,硕士生,从事卫星通信研究.orcid.org/0000-0002-1957-6363.E-mail:xupanpan@zju.edu.cn
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引用本文:

徐盼盼, 张朝杰, 娄延年, 徐九凌. 基于FPGA的全数字时钟生成方法[J]. 浙江大学学报(工学版), 2017, 51(12): 2341-2347.

XU Pan-pan, ZHANG Chao-jie, LOU Yan-nian, XU Jiu-ling. FPGA-based all-digital clock generation method. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(12): 2341-2347.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2017.12.005        http://www.zjujournals.com/eng/CN/Y2017/V51/I12/2341

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